With the spread of portage personal computers such as notebook-type PCs, computer systems are increasingly required to be small and light, and to have low power consumption. Since external storage systems using a semiconductor memory do not need a mechanical drive system as is required in magnetic disk devices, they can operate with low power consumption and at high speed. Further, since such external storage systems are constituted in the form of small memory modules, they are smaller and lighter than magnetic disks, a large degree of freedom can be exercised in determining their shape, and they can easily be implemented in a card form. A flash memory with an en-block erase capability (also called a flash EEPROM) has been developed as a memory suitable for such applications. An outline of this type of flash memory is described in Richard D. Pashley et al., "Flash memories: the best of two worlds," IEEE Spectrum, December 1989, pp 30-33.
As in the case of the DRAM, in a flash memory, a memory element (i.e., memory cell) of 1 bit consists of one transistor. There, the flash memory can be highly integrated, and is expected to have a bit price the same as or lower than that of the DRAM, depending on the future market, which means that it will be a low-cost, large-capacity memory. Since the memory element is nonvolatile, battery backup is not needed. However, the programming of memory bits is performed on a one-way basis only; that is, all changes must be either 0 to 1 or 1 to 0. In order to change a bit value in the opposite direction, all the bit values of a memory block must be made 0 or 1 by en-bloc erasure, which requires a special procedure such as a verify operation.
It may be incidentally mentioned that a conventional flash memory is required to have random access capability in order to be compatible with normal ROM. To this end, like DRAM and other types of memory, the conventional flash memory employs, as a measure for avoiding the use of defective memory cells in a chip, a redundant circuit for replacing, by the use of an address conversion circuit, an entire word line or bit line associated with a defective memory cell with another word line or bit line. This architecture can provide high-speed processing because all address conversion is performed by hardware within the chip. Therefore, this technique is indispensable in memory chips in which random access speed is an important factor. At present, since the yield of produced chips largely depends on the redundant efficiency of the memory cells with the use of the redundant circuit, it is desirable to employ as many redundant word lines or bit lines as possible to improve the yield.
However, the conventional architecture requires one address conversion circuit for the replacement of one word or bit line, which greatly affects the chip area. Furthermore, it is impossible in practice to prepare a large number of redundant word or bit lines. In actual practice, only two to four redundant word or bit lines are employed for 512 to 1,024 word or bit lines, which does not provide a sufficient redundancy efficiency. Since no means is provided for invalidating a work or bit line that is not recovered by a redundant one, the existence of only one such a word or bit line will cause the entire chip to be discarded as defective.
Published Unexamined Japanese Patent Application No. 2-292798 discloses an error correction algorithm in which redundant cells and a means for replacing either one or else two or more defective cells with a corresponding number of redundant cells are provided to correct for errors that occur when a cell array of a flash EEPROM includes defective cells. The cell array is divided into a plurality of sectors, and the cells are erased en bloc on a sector basis; each cell cannot be erased individually. The redundant cells are provided in the same sector as the defective cells that are to be replaced with the redundant cells. Furthermore, a defect map for storing defect pointers for associating addresses of defective cells with those of redundant cells is also provided in the same sector as the defective cells.
Simply employing this type of memory chip configuration will cause a problem in that the information contained in the defect map is also lost at the time of sector erasure. Moreover, cases in which a defect exists in the area of the defect map cannot be accommodated, which may cause miscorrection. An error correction code (ECC) is usually employed to protect the defect map. However, when an ECC serves an entire sector, sufficient performance will not be provided, and, above all, there are no redundant cells used.
In many conventional flash memories the entire chip is an erase unit. Even in flash memories in which small parts of a chip are made into erase units, respective erase units are connected to different word lines. The sharing of a word line by two physically separated erase units, which is proposed herein, is not known.
As described above, the problem of how to add an efficient redundant architecture to a memory chip is an important consideration that will directly influence production yield, and thus the production cost of the chip. Furthermore, in the present circumstances, in order to create a better redundant architecture, it is necessary to consider the entire system in addition to the inside of a chip.